1. Field of the Invention
The present invention relates in general to a method of processing signals. In particular, the present invention relates to a method of processing signals of an LCM (LCD Module, Liquid Crystal Display Module) timing controller.
2. Description of the Related Art
According to U.S. Pat. No. 5,856,818, as shown in FIG. 1, an LCM 10 has a timing controller 12 which generates signals, such as a gate clock signal CPV, start vertical signals STV1, STV2, or a gate-on enable signal OE for a gate driver 16 and a source driver 18 of a LCD panel 14 after receiving a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSYNC, and a data enable signal DE.
In another mode, as shown in FIG. 2, the timing controller 12 which generates signals, such as a gate clock signal CPV, start vertical signals STV1, STV2, or a gate-on enable signal OE for a gate driver 16 and a source driver 18 of a LCD panel 14 after receiving a data enable signal DE.
In the method of processing signals of a conventional timing controller, as shown in FIG. 3 or FIG. 4, a next control signal is generated according to a memory value of a previous horizontal or vertical cycle. When an LCD module is in DE mode or in the mode of three synchronizing signals HSYNC, VSYNC, DE, a conventional timing controller decodes control signals according to the memory values of horizontal and vertical cycles. For example, in a vertical blank period VB (v-blank) of the data enable signal DE, the start vertical signals STV1, STV2 are generated according to the gate clock signal CPV.
Refer to FIG. 5 and FIG. 6 which correspond to the methods of processing signals in FIG. 3 and FIG. 4 respectively. The timing controller processes signals according to the memory values of horizontal and vertical cycles, such as the vertical blank period VB (v-blank), the gate clock signal CPV. Since signals of the horizontal and vertical cycles are unstable, the horizontal or vertical cycle of a video signal is caused to vary. As far as the timing controller is concerned, the cycle variance incurs erroneous operations of control signals. For example, the gate clock signal CPV does not generate the start vertical signals STV1, STV2 until after the vertical blank period VB(v-blank) of the data enable signal DE, and the display frame of the LCD module is therefore caused to jitter or bounce. The start vertical signals STV include: a first start vertical signal STV1, for determining a start scan location of a frame; and a second start vertical signal STV2, for offsetting the flicker and display brightness.